This application claims the priority of Korean Patent Application No. 2003-58287, filed on Aug. 22, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a highly integrated semiconductor device and a method of manufacturing the highly integrated semiconductor device, and more particularly, to a highly integrated semiconductor device with a silicide layer that can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device.
2. Description of the Related Art
As the degree of integration of a semiconductor device increases, the area and line width of the semiconductor device decreases, resulting in an increase of an interconnection resistance and a contact resistance of the semiconductor device.
Such an increase in resistance reduces the operating speed of the semiconductor device.
To reduce the interconnection resistance and contact resistance, a method of forming a self-aligned silicide (SALICIDE) layer on a gate electrode, a source region, and a drain region of a metal oxide semiconductor (MOS) transistor has been suggested in Silicon processing for the VLSI Era (Vol. 4, page 604).
A conventional highly integrated semiconductor device comprising a self-aligned silicide layer will be described with reference to FIGS. 1 and 2.
Referring to FIG. 1, a gate insulating layer 15 and a polysilicon layer 18 are sequentially deposited on a semiconductor substrate 10, for example, a silicon substrate, and predetermined portions of the gate insulating layer 15 and the polysilicon layer 18 are patterned to form a gate electrode 20. Low concentration impurity ions are implanted into predetermined portions of the semiconductor substrate 10 on both sides of the gate electrode 20 to form lightly doped drain (LDD) regions 25a and 25b. Next, an insulating spacer 30 is formed along both sidewalls of the gate electrode 20, and heavily doped regions 35a and 35b are formed in predetermined portions of the semiconductor substrate 10 on both sides of the spacer 30, thereby forming a source region 40a and a drain region 40b. Next, a transition metal layer (not shown) is deposited on the resultant structure, and a heat treatment is performed. The gate electrode 20, the source region 40a, and the drain region 40b, which are made of silicon, react with the transition metal layer, such that a silicide layer 45 is formed on the gate electrode 20, the source region 40a, and the drain region 40b. Next, unreacted portions of the transition metal layer are removed. Since the silicide layer 45, which has a low resistance, is formed on the gate electrode 20, the source region 40a, and the drain region 40b, which are to be connected to a metal layer later, an interconnection resistance and a contact resistance are reduced.
Referring to FIG. 2, an interlayer insulating layer 50 is deposited on the resultant structure of FIG. 1, and is etched until the source region 40a and the drain region 40b are exposed, thereby forming a contact hole 55a. 
However, as the degree of integration of the semiconductor device increases, the areas of the source region 40a and the drain region 40b decrease. Because of a lack of a margin necessary for the contact hole, misalignment may occur during a photolithography process performed to form the contact hole. If misalignment occurs, a contact hole 55 passing through the spacer 30 may be formed, thereby exposing the LDD region 25a, as shown in FIG. 2. Since the LDD region 25a exposed by the contact hole 55 has a relatively low impurity concentration and a high resistance, a contact resistance between the LDD region 25a and the metal layer (not shown) increases when the LDD region 25a contacts the metal layer later.
Furthermore, with the reduced line width of the gate electrode in the highly integrated semiconductor device, the depths of the source region 40a and the drain region 40b are also decreasing. As a consequence, a design rule of less than 0.1 μm requires a junction depth less than approximately 800 Å.
If the silicide layer 45 is formed on the source region 40a and the drain region 40b having a shallow junction depth, the silicide layer must also be thin, and the silicon of which the source region 40a and the drain region 40b are made is mostly used to form the silicide layer 45, causing a junction leakage current.